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february 2011 doc id 16082 rev 5 1/46 1 L99MD02 hexa half-bridge driver with spi control for automotive applications features 6 half bridges r on = typ.0.9 (hs), 0.64 (ls) at t j =25c current limit of each output at minimum 0.8 a internal pwm generation pwm mode option for all half bridges for hold current two current monitor outputs spi interface for data communication temperature warning all outputs overtemperature protected all outputs short circuit protected v cc supply voltage 3.0 to 5.3 v very low current consumption in standby mode typ. 5 a v s operating range compliant: 6 ? 18 v applications dc motor driver intended to drive hvac flaps description the L99MD02 ic is a 6 x half bridge driver for automotive applications. the device is intended to drive dc-motors. it is possible to drive 3 dc-motors simultaneously or up to 5 dc-motors sequentially. the integrated 24 bit standard serial peripheral interface (spi) controls all outputs and provides diagnostic information: normal operation, open-load in on-state, overcurrent, temperature warning and overtemperature. table 1. device summary package order code tube tape and reel powersso- 36 L99MD02xp L99MD02xptr powersso-36 *$3*&)7 www.st.com
contents L99MD02 2/46 doc id 16082 rev 5 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 power supply: v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 power supply: v sa , v sb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.8 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 8 2.9 v s , v sa , v sb monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.10 open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.11 overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.12 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 spi electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 spi timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.2 serial data input (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.3 serial data output (sdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.4 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L99MD02 contents doc id 16082 rev 5 3/46 6.2 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.2 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.6 read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 spi control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1 ecopack ? package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2 powersso-36? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
list of tables L99MD02 4/46 doc id 16082 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. v s , v sa , v sb monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. over and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. current monitor dynamic characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 table 13. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 14. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 15. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 16. dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 17. command byte (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19. operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 21. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22. ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23. rom memory map (access with oc0 and oc1 set to ?1?) . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. control status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 25. control register 1 (read/write); address 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 26. control register 3 (read/write); address 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 27. control register 4 (read/write); address 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 28. ratio for curr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 29. ratio for curr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 30. control register 5 (read/write); address 05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 31. control register 6 (read/write); address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 32. status register 0 (read only); address 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 table 33. status register 1 (read only); address 11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 34. status register 2 (read only); address 12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 35. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 36. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
L99MD02 list of figures doc id 16082 rev 5 5/46 list of figures figure 1. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. pin connection (top view-not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. output turn-on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 5. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. spi frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. indication of the global error flag on sdo when csn is low and sck is stable . . . . . . . . . 27 figure 10. driving 3 dc-motors simultaneously. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. driving 5 dc-motors sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 12. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13. powersso-36 thermal impedance junction ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. powersso-36? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 15. powersso-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16. powersso-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
block diagram L99MD02 6/46 doc id 16082 rev 5 1 block diagram figure 1. detailed block diagram /2*,& *1' 9 v 63, 08; 9 v% 9 ff 9rowdjh0rqlwrulqj 3*1' 287 287 &855 &855 6&. '2 ', &61 (1 9 ff 9 ff 9 v$ 9 v% &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg 287 287 287 9 v$ 3*1' 9 ff 9 ff &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg &xuuhqw 0rqlwru &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg 287 *$3*&)7
L99MD02 overview doc id 16082 rev 5 7/46 2 overview 2.1 power supply: v cc the supply voltage v cc (3.3 v / 5 v) supplies the whole device. in case of power-on (v cc increases from undervoltage to v por off = 2.75 v, typical) the circuit is initialized by an internally generated power-on reset (por). if the voltage v cc decreases under the minimum threshold (v por on = 2.55 v, typical), the outputs are switched off in 3-state (high impedance). the status registers are cleared and the control registers are reset to their default. figure 2. power on reset 2.2 power supply: v sa , v sb each v sa and v sb supplies the half bridges independently. v sa out 1 to out 3 v sb out 4 to out 6 2.3 standby mode the standby mode of the L99MD02 is activated by en pin to low. the inputs and outputs are switched off. the status registers are cleared and the control registers are reset to their default values. in the standby mode the current consumption is typically 5 a. $*9 (1
overview L99MD02 8/46 doc id 16082 rev 5 2.4 pwm mode pwm frequency typ. 100 hz. duty cycle (spi 2bit): 15%, 30%, 45% and 60%. each half-bridge is independently addressable (spi 8bit). 2.5 current monitor the current monitor output sources a current image at the current monitor output which has a programmable ratio (1/250, 1/500, 1/750, 1/1000) of the instantaneous current of the selected half bridge (high side or low side). via spi it can be programmed which of the outputs will be multiplexed to the current monitor output. the current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open-or overload condition. for example this can be used to detect the motor state (starting, free-running, stalled). 2.6 inductive loads each half bridge is built by an internally connected high-side and a low-side power dmos transistor. due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs 2.7 diagnostic functions all diagnostic functions (over/open-load, temperature warning and thermal shutdown, over/undervoltage) are internally filtered and the condition has to be valid for at least 32 s (open-load: typ. 2 ms, respectively) before the corresponding status bit in the status registers will be set. the filters are used to improve the noise immunity of the device. open- load and temperature warning function are intended for information purpose and will not change the state of the output drivers. on contrary, the overload and thermal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. the microcontroller has to clear the overcurrent status bit to reactivate the corresponding driver. 2.8 temperature warning and thermal shutdown if the junction temperature rises above t jtwon a temperature warning flag is set and is detectable via the spi. if the junction temperature increases above the second threshold t jsdon , the thermal shutdown bit will be set and power dmos transistors of all output stages are switched off to protect the device. temperature warning flag and thermal shutdown bits are latched. in order to reactivate the output stages, the junction temperature must decrease below t jsdon -t jsdhys and the thermal shutdown bit has to be cleared by the microcontroller.
L99MD02 overview doc id 16082 rev 5 9/46 2.9 v s , v sa , v sb monitoring 2.10 open-load detection the open-load detection monitors the load current in each activated output stage. if the load current is below the open-load detection threshold for at least 2 ms (t dol ) the corresponding open-load bit is set in the status register. due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open-load status without changing the mechanical/ electrical state of the loads. 2.11 overload detection in case of an overcurrent condition, a flag is set in the corresponding status register. if the overcurrent signal is valid for at least t isc = 32 s, the overcurrent flag is set and the corresponding switch is switched off to reduce the power dissipation and to protect the integrated circuit. the microcontroller has to clear the status bit to reactivate the corresponding driver. 2.12 cross-current protection the device is cross-current protected by an internal delay time. if one driver (ls or hs) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. after the cross-current protection time is expired the slew-rate limited switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. due to this behavior it is v s undervoltage: status bit will be set. have to be cleared via spi. all outputs will be switched off. v s overvoltage: status bit will be set. has to be cleared via spi. all outputs will be switched off (default). can be deactivated via spi. v sa undervoltage: status bit will be set. has to be cleared via spi. out 1 to out 6 will be switched off. v sb undervoltage: status bit will be set. has to be cleared via spi. out 1 to out 6 will be switched off. table 2. v s , v sa , v sb monitoring ?typ out x v s undervoltage 5.7 v status + off v s overvoltage 22.0 v status + (off or mask) v sa undervoltage 5.7 v status + off v sb undervoltage 5.7 v status + off
overview L99MD02 10/46 doc id 16082 rev 5 always guaranteed that the previously activated driver is totally turned-off before the opposite driver will start to conduct. if wrong spi commands try to turn-on both driver (ls and hs) simultaneously, the high side and the low side will be (or stay) deactivated (3- state).
L99MD02 pin definitions and functions doc id 16082 rev 5 11/46 3 pin definitions and functions table 3. pin description pin symbol function 1, 18, 19, 36 p gnd power ground: reference potential 9 a gnd analog ground: reference potential 27 d gnd digital ground: reference potential 6, 10, 13, 21, 23, 25, 32, 34 n.c. not connected exposed pad: reference potential connected to p gnd 2, 3, 16, 17, 20, 35 out 1 -6 half bridge-output: the output is built by a high-side and a low-side switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to v sx , low-side driver from p gnd to output). 29 v cc logic voltage supply 3.3v / 5v for this input a ceramic capacitor as close as possible to gnd is recommended 4, 5, 33 v sa power supply voltage for out 1 to 3 (external reverse protection required): for this input a ceramic capacitor as close as possible to gnd is recommended. important: for the capability of driving the full current at the outputs all pins of v sa must be externally connected! 14, 15, 22 v sb power supply voltage for out 4 to 6 (external reverse protection required): for this input a ceramic capacitor as close as possible to gnd is recommended. important: for the capability of driving the full current at the outputs all pins of v sb must be externally connected! 11 v s v s 12 v s v s supply and monitoring 7, 8 curr1 / 2 current monitor 1 / 2 31 en enable enable the L99MD02 28 di spi data in the input requires cmos logic levels and receives serial data from the microcontroller. the data is a 24 bit control word and the most significant bit (msb) is transferred first. 26 do spi data out the diagnosis data is available via the spi and this 3- state output. the output will remain in 3-state, if the chip is not selected by the input csn (csn = high) 24 csn spi csn chip select not (active low) this input is low active and requires cmos logic levels. the serial data transfer between the L99MD02 and micro controller is enabled by pulling the input csn to low level. 30 sck spi serial clock input this input controls the internal shift register of the spi and requires cmos logic levels.
pin definitions and functions L99MD02 12/46 doc id 16082 rev 5 figure 3. pin connection (top view-not in scale) 3rzhu662 3 *1' 287 287 9 6$ 9 6$ 1& &855 &855 $ *1' 1& 9 6 9 6 1& 9 6% 9 6% 287 287 3 *1' 3 *1' 287 1& 9 6$ 1& (1 6&. 9 && ', ' *1' '2 1& &61 1& 9 6% 1& 287 3 *1' *$3*&)7
L99MD02 electrical specifications doc id 16082 rev 5 13/46 4 electrical specifications 4.1 absolute maximum ratings note: all maximum ratings are absolute ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit! 4.2 esd protection 4.3 thermal data table 4. absolute maximum ratings symbol parameter value unit v s dc supply voltage -0,3?28 v single pulse t max < 400 ms 40 v v sa v sb dc supply voltage -0,3?38 v single pulse t max < 400 ms 40 v v cc stabilized supply voltage, logic supply -0.3 to 5.5 v en di do sck csn digital input / output voltage -0.3 to v cc + 0.3 v curr1/2 current monitor output -0.3 to v cc + 0.3 out 1-6 output current capability 2 a table 5. esd protection parameter value unit all pins 2 (1) 1. hbm according to eia/jesd22-a114-e. kv output pins: out1 ? 6, v s , v sa , v sb , 4 (2) 2. hbm with all unzapped pins grounded. kv table 6. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 150 c
electrical specifications L99MD02 14/46 doc id 16082 rev 5 4.4 electrical characteristics v s = 6 to 18 v, v cc = 3.0 to 5.3 v, t j = -40 to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 7. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t jtw on temperature warning threshold junction temperature t j i ncreasing - - 150 c t jsd on thermal shutdown threshold junction temperature t j increasing - - 170 c table 8. supply symbol parameter test condition min. typ. max. unit v sa /v sb operating supply voltage range 6 38 v i s v sa / v sb dc supply current v sx = 13 v, v cc = 5.0 v en = high outputs floating 0.5 2 ma i vs v s supply current v s = 13 v, v cc = 5 v en = high 1.5 4 ma i vsx v sx (v s , v sa , v sb ) quiescent supply current v sx = 13 v, v cc = 5 v en = low t te s t = -40, 25 c outputs floating 3 10 a t te s t = 130 c 6 20 a v cc operating supply voltage range 3,0 5,3 v i cc v cc dc supply current v sx = 13 v, v cc = 5.0 v en = high 1 3 ma v cc quiescent supply current v s = 13 v, v cc = 5.0 v csn = v cc en = low outputs floating 5 20 a table 9. over and undervoltage detection symbol parameter test condition min. typ. max. unit v por off power-on-reset threshold v cc increasing 3.0 v v por on power-on-reset threshold v cc decreasing 2.3 v v por hyst power-on-reset hysteresis v por off - v por on 0.2 v v suv off v s uv-threshold voltage v s increasing 6.0 6.7 v
L99MD02 electrical specifications doc id 16082 rev 5 15/46 v suv on v s uv-threshold voltage v s decreasing 5.4 6 v v suv hyst v s uv-hysteresis v suv off -v suv on 0.35 0.5 v v sauv off v sa uv-threshold voltage v sa increasing 5.95 6.7 v v sauv on v sa uv-threshold voltage v sa decreasing 5.4 6 v v sauv hyst v sa uv-hysteresis v sauv off -v sauv on 0.35 0.5 v v sbuv off v sb uv-threshold voltage v sb increasing 6.0 6.7 v v sbuv on v sb uv-threshold voltage v sb decreasing 5.4 6 v v sbuv hyst v sb uv-hysteresis v sbuv off -v sbuv on 0.35 0.5 v v sov on v s ov-threshold voltage v s increasing 24 v v sov off v s ov-threshold voltage v s decreasing 18 v v sov hyst v s ov-hysteresis v sov on -v sov off 0.75 1 v table 10. switches symbol parameter test condition min. typ. max. unit r on hs 1-6 on resistance v sa / v sb to out 1-6 t j = 25 c, i out 1-6 = -0.25 a 900 1200 m t j = 125 c, i out 1-6 = -0.25 a 1300 1800 m r onlshc 1-6 on resistance out 1-6 to gnd in hc mode t j = 25 c, hc = 1 i out 1-6 = 0.25a 700 1000 m t j = 125 c, hc = 1 i out 1-6 = 0.25 a 1000 1500 m r onlslc 1-6 on resistance out 1-6 to gnd in lc mode t j = 25 c, hc = 0 i out 1-6 = 0.125 a 1200 1800 m t j = 125 c, hc = 0 i out 1-6 = 0.125 a 2000 2800 m i schs1-6 hs overcurrent protection v s = 13.5 v 0.8 1.4 a i sclshc1-6 ls overcurrent protection in hc mode v s = 13.5 v, hc=1 0.8 1.4 a i sclslc1-6 ls overcurrent protection in lc mode v s = 13.5 v, hc=0 0.4 0.7 a t d on1-6 h output delay time, hs switch on v s = 13.5 v, r load = 52 10 25 80 s t d off1-6 h output delay time, hs switch off v s = 13.5 v, r load = 52 50 100 300 s t d on1-6 l output delay time, ls switch on v s = 13.5 v, r load = 52 5 15 80 s t d off1-6 l output delay time, ls switch off v s = 13.5 v, r load = 52 50 100 300 s table 9. over and undervoltage detection (continued) symbol parameter test condition min. typ. max. unit
electrical specifications L99MD02 16/46 doc id 16082 rev 5 figure 4. output turn-on/off delays and slew rates t d lh /t d hl cross current protection time 20 200 400 s i qlh switched-off output current hs out 1-6 v out1-6 = 0 v -2 a i qll switched-off output current ls out 1-6 v out1-6 = v s 2a i oldhs1-6 open-load detection current hs out 1-6 t amb = -40 c 8 30 60 ma t amb = 25 c to 125 c 10 30 60 ma i oldlshc1-6 open-load detection current ls out 1-6 in hc mode hc bit set to 1; t amb = -40 c 4.5 30 65 ma hc bit set to 1; t amb = 25 c to 125 c 83060ma i oldlslc1-6 open-load detection current ls out 1-6 in lc mode hc bit set to 0; t amb = -40 c 1.8 15 35 ma hc bit set to 0; t amb = 25 c to 125 c 41530ma t dol minimum duration of open-load condition to set the status bit 500 2000 3000 s t isc minimum duration of overcurrent condition to switch off the driver 10 32 100 s dv out1-6 /dt slew rate of out 1-6 v s = 13.5 v, r load = 52 0.1 0.25 0.5 v/s table 10. switches (continued) symbol parameter test condition min. typ. max. unit *1' *1' / rz6lgh + ljk6lgh 9 287; 9 287; w g21[/+ g9rxw[gw *1' /rz6lgh +ljk6lgh 9 287; 9 287; w g2))[/+ g9rxw[gw *1' $*9
L99MD02 electrical specifications doc id 16082 rev 5 17/46 table 11. current monitor output symbol parameter test condition min. typ. max. unit v curr1/2 functional voltage range v cc = 5 v 0 v cc -1 v i currhsls250 hs/ls current monitor output ratio: i curr1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v, v cc = 5 v; prog. via spi, i max =800ma 1/250 i currhsls500 hs/ls current monitor output ratio: i curr1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v v cc = 5 v; prog. via spi, i max =800ma 1/500 i currhsls750 hs/ls current monitor output ratio: i curr1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v v cc = 5 v; prog. via spi, i max =800ma 1/750 i currhsls1000 hs/ls current monitor output ratio: i curr1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v v cc = 5 v; prog. via spi, i max =800ma 1/1000 i currlslc125 ls current monitor output ratio in lc mode: i curr1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v v cc = 5 v; prog. via spi, hc=0; i max =400ma 1/125 i currlslc250 ls current monitor output ratio in lc mode: i currlslc1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v v cc = 5 v; prog. via spi, hc=0; i max =400ma 1/250 i currlslc375 ls current monitor output ratio in lc mode: i curr1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v v cc = 5v; prog. via spi, hc = 0; i max = 400ma 1/375 i currlslc500 ls current monitor output ratio in lc mode: i curr1/2 / i out 1-6 0v <= v curr1/2 <= v cc -1v v cc = 5v; prog. via spi, hc = 0; i max =400ma 1/500 i currhs1/2 acc hs current monitor accuracy 0v v curr1/2 v cc -1v, v cc =5v; i out 1-6 max =0.8a ; (fs = full scale = 800 ma*current ratio); t j =-40c 4% + 1%fs 10% + 3%fs - 0v v curr1/2 v cc -1v, v cc =5v; i out 1-6 max =0.8a; (fs = full scale = 800 ma*current ratio); t j = 25 c to 125 c 4% + 1%fs 8% + 2%fs i currlshc1/2 acc ls current monitor accuracy in hc mode 0v v curr1/2 v cc -1v; v cc =5v; 0.4a i out1-6 0.8 a; (fs = full scale = 800 ma*current ratio) 4% + 1%fs 10% + 3%fs - i currlslc1/2 acc ls current monitor accuracy in lc mode 0v v curr1/2 v cc -1v; v cc =5v; i out 1-6 max = 0.4 a; (fs = full scale = 800 ma*current ratio) 4% + 1%fs 10% + 3%fs -
electrical specifications L99MD02 18/46 doc id 16082 rev 5 table 12. current monitor dynamic characteristics symbol parameter test condition min. typ. max. unit t d-cm output to current monitor delau time i out from 100 ma to 200 ma; t d-cm measured from 50% i out to 50% icm ?2?s table 13. oscillator symbol parameter test condition min. typ. max. unit f clk internal clock frequency 2.8 4 5.2 mhz
L99MD02 spi electrical characteristics doc id 16082 rev 5 19/46 5 spi electrical characteristics v s = 6 to 18 v, v cc = 3.0 to 5.3 v, t j = -40 to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin table 14. dc characteristics symbol parameter test condition min. typ. max. unit sdi, sck, csn, en v il input low voltage 0.3 v cc v v ih input high voltage 0.7 v cc v i csn in pull up current at input csn v csn = 1.5 v; v cc = 5 v 8 20 40 a i sck in pull down current at input sck v sck = 1.5 v; v cc = 5 v 10 25 50 a i di in pull down current at input di v di = 1.5 v; v cc = 5 v 10 25 50 a r en in pull down resistor at input en v en = 1.5 v; v cc = 5 v 25 50 115 k sdo v ol output low voltage i out = 2 ma 0.2 0.4 v v oh output high voltage i out = +2 ma v cc - 0.4 v cc - 0.2 v i dolk 3-state leakage current v csn = v cc , 0 v < v cc -10 10 a table 15. ac characteristics symbol parameter test condition min. typ. max. unit sdo, sdi, sck, csn, en c out (1) 1. guaranteed by design. output capacitance (sdo) v out = 0 v to 5 v - - 10 pf c in input capacitance (sdi) v in = 0 v to 5 v - - 10 pf input capacitance (other pins) v in = 0 v to 5 v - - 10 pf table 16. dynamic characteristics (1) symbol parameter test condition min. typ. max. unit t en en high setup time 100 s t scsn csn setup time before sck rising 400 ns t hcsn csn high time 2 s
spi electrical characteristics L99MD02 20/46 doc id 16082 rev 5 t csnqv csn falling until sdo valid c out = 100 pf 100 ns t csnqt csn rising until sdo 3-state c out = 100 pf 150 ns t ssck sck setup time before csn rising 50 ns t ssdi sdi setup time before sck rising 40 ns t hsck sck high time 200 ns t lsck sck low time 200 ns t sckqv sck falling until sdo valid c out = 100 pf 150 ns t qlqh output rise time c out = 100 pf 20 % - 80 % v cc 110 ns t qhql output fall time c out = 100 pf 20 % - 80 % v cc 110 ns f spi spi frequency 1 mhz 1. see section 5.1: spi timing parameter definition table 16. dynamic characteristics (1) (continued) symbol parameter test condition min. typ. max. unit
L99MD02 spi electrical characteristics doc id 16082 rev 5 21/46 5.1 spi timing parameter definition figure 5. spi timing w &6149 &61idoolqjxqwlo6'2ydolg w 6&.49 6&.ulvlqjxqwlo6'2ydolg w 6&61 &61vhwxswlphehiruh6&.ulvlqj w 66', 6',vhwxswlphehiruh6&.ulvlqj w +6&. plqlpxp6&.kljkwlph w /6&. plqlpxp6&.orzwlph w +&61 plqlpxp&61kljkwlph w &6147 &61ulvlqjxqwlo6'2wulvwdwh w 66&. 6&.vhwxswlphehiruh1&6ulvlqj &6 1 6' 2 'dwdrxw w &6147 w 6&.49 6& . 'dwdrxw w +6&. w /6&. w 6&61 w +&61 'dwdlq 'dwdlq w 66', 6' , w &6149 w 66&. $*9
spi electrical characteristics L99MD02 22/46 doc id 16082 rev 5 figure 6. serial output timing *$3*06
L99MD02 functional description of the spi doc id 16082 rev 5 23/46 6 functional description of the spi 6.1 signal description 6.1.1 serial clock (sck) this input signal provides the timing of the serial interface. data present at serial data input (sdi) is latched on the rising edge of serial clock (sck). data on serial data out (sdo) is shifted out at the falling edge of serial clock (see figure 7 ). the spi can be driven by a microcontroller with its spi peripherals running in following mode: cpol = 0 and cpha = 0 (see figure 7 ). 6.1.2 serial data input (sdi) this input is used to transfer data serially into the device. it receives the data to be written. values are latched on the rising edge of serial clock (sck). 6.1.3 serial data output (sdo) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (sck). sdo also reflects the status of the (bit 7 of the ) while csn is low and no clock signal is present 6.1.4 chip select not (csn) when this input signal is high, the device is deselected and serial data output (sdo) is high impedance (3-state). driving this input low enables the communication. the communication must start and stop on a low level of serial clock (sck). figure 7. clock polarity and clock phase &32/&3+$ &61 6&. 6', 6'2 06% /6% 06% /6% +, +, *$3*&)7
functional description of the spi L99MD02 24/46 doc id 16082 rev 5 figure 8. spi frame structure 6.2 spi communication flow 6.2.1 general description the proposed spi communication is based on a standard spi interface structure using csn (chip select not), sdi (serial data in), sdo (serial data out/error) and sck (serial clock) signal lines. maximum spi frequency is 1 mhz. at the beginning of each communication the master reads the register (rom address 3eh) of the slave device. this 8-bit register indicates the spi frame length (24 bit for the L99MD02) and the availability of additional features. each communication frame consists of an instruction byte which is followed by 2 data bytes ( figure 8 ). &61 6'2 6', 06% 06% /6% /6% :ulwh 2shudwlrq &61 6'2 6', *oredo6wdwxv %\wh elw 06% 06% /6% /6% 'dwd 5hdg 2shudwlrq 06% /6% 06% /6% elw &rppdqg %\wh elw *oredo6wdwxv %\wh elw &rppdqg %\wh elw 'rq?wfduh elw 'dwd suhylrxvfrqwhqwriuhjlvwhu 'dwd elw *$3*&)7
L99MD02 functional description of the spi doc id 16082 rev 5 25/46 the data returned on sdo within the same frame always starts with the register. it provides general status information about the device. it is followed by 2bytes (i.e. ?in-frame-response?, figure 8 ). for write cycles the register is followed by the previous content of the addressed register. for read cycles the register is followed by the content of the addressed register. 6.2.2 command byte each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation (, , , ) and a 6 bit address. the and operations allow access to the ram of the device, i.e. write to control registers or read status information. a operation addressed to a device specific status register will read back and subsequently clear this status register. a operation with address 3fh clears all status registers at a time and reads back the register. a operation addressed to an unused ram address register will be identical to a operation (in case of unused ram address, the second byte will be equal to 00h). allows access to the rom area which contains device related information such as the product family, product name, silicon version and register width. table 17. command byte (8 bit) operating code address bit 23 22 21 20 19 18 17 16 name oc1 oc0 a5 a4 a3 a2 a1 a0 table 18. data byte data byte 1 data byte 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 19. operating code definition oc1 oc0 meaning 0 0 0 1 1 0 1 1
functional description of the spi L99MD02 26/46 doc id 16082 rev 5 the is generated by an or-combination of all failure events of the device (i.e. bit 0 to bit 6 of the ). table 20. global status byte bit description polarity comment 0 software reset or under/ overvoltage active high depend on bit 5 of : 1 overcurrent detected active high set by any overcurrent event 2 open-load detected active high set by any open-load event 3 temp warning active high 4 thermal shutdown / chip overload active high 5 not (chip reset or communication error) active low activated by all internal reset events that change device state or configuration registers (e.g. software reset, v cc under- voltage, etc.). the bit will be set after a valid communication with any register. this bit is initially ?0? and will be set to ?1? by a valid spi communication 6 communication error active high bit is set if the number of clock cycles during csn = low does not match with the specified frame width or if an invalid bus condition is detected (sdi stuck at 1 or 0). 7 global error flag active high logic or combination of all failures in the . bit 5 bit 0 0 set if software reset (sdi stuck at 1 or 0) 1 logical or of the under- / overvoltage status bits
L99MD02 functional description of the spi doc id 16082 rev 5 27/46 figure 9. indication of the global error flag on sdo when csn is low and sck is stable the bit 0 of the is a combination of an under/overvoltage warning and a software warning: if the bit 5 is one (this is the standard after a correct spi communication), bit 0 is the logical or of all under- and overvoltage status bits. on the other hand, if there has been an spi communication error or a chip reset (bit 5 is zero), then bit 0 gives a better indication about the spi error: an sdi stuck-at error will lead to a software reset and will set bit 0, while a clock pulse error only sets the communication error bit, clears bit 5 and will clear also bit 0. this leads to the following table of possible states (assuming there is no under/overvoltage, overcurrent, openload or thermal error): writing to the selected data input register is only enabled if exactly one frame length is transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame, the complete frame will be ignored and a spi frame error is signaled in the global status register. this safety function is implemented to avoid an unwanted activation of output stages by a wrong communication frame. &61 6&. 6', 6'2 &61kljkwrorzdqg6&.vwd\vorz*oredo(uuru)odjelwri ?*oredo6wdwxv%\wh3lvwudqvihuhgwr6'2 wlph wlph wlph wlph 6'2*oredo(uuru)odj%lwri?*oredo6wdwxv%\wh3zloovwd \dvorqj&61lvorz *() *$3*06 table 21. reset state description global status en = 0 (power on reset) all registers reset outputs switched off (3-state) 1000 0000 clock cycles != 24 ignore frame no reset 1100 0000 sdi always 0 software reset outputs switched off 1100 0001 sdi always 1 software reset outputs switched off 1100 0001
functional description of the spi L99MD02 28/46 doc id 16082 rev 5 for read operations, the bit in the will be set, but the register to be read will still be transferred to the sdo pin. if the number of clock cycles is smaller than the frame width, the data at sdo will be truncated. if the number of clock cycles is larger than the frame width, the data at sdo will be filled with ?0? bits. due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ics is recommended. note: as the frame width is 24 bits, an initial read of using a 16 bits communication will set the of the . a subsequent correct length transaction is necessary to correct this bit. 6.3 write operation oc0, oc1: operating code (00 for ?write? mode). the write operation starts with a command byte followed by 2 data bytes. for write cycles the register is followed by the previous content of the addressed register. the ram memory area consists of 16 bit registers. all unused ram addresses will be read as ?0?. failures are indicated by activating the corresponding bit of the register. note: ram address 00h is unused. an attempt to access this address is recognized as a communication line error (?data-in stuck to gnd?) and all internal registers will be cleared (software reset). 6.4 read operation oc0, oc1: operating code (01 for ?read? mode). the read operation starts with a command byte followed by 2 data bytes. the content of the data bytes is ?don?t care?. the content of the addressed register is shifted out at sdo within the same frame (?inframe response?). the returned data byte represents the content of the register to be read. failures are indicated by activating the corresponding bit of the register. 6.5 read and clear status operation oc0, oc1: operating code (10 for ?read and clear status? mode). the ?read and clear status? operation starts with a command byte followed by 2 data bytes. the content of the data bytes is ?don?t care?. the content of the addressed status register is transferred to sdo within the same frame (?in-frame response?) and is subsequently cleared. a ?read and clear status? operation with address 3fh clears all status registers simultaneously.
L99MD02 functional description of the spi doc id 16082 rev 5 29/46 a operation addressed to an unused ram address will be identical to a operation (in case of unused ram address, the second byte will be equal to 00h). the returned data byte represents the content of the register to be read. failures are indicated by activating the corresponding bit of the register. 6.6 read device information oc0, oc1: operating code (11 for ?read device information mode) the device information is stored at the rom in the rom memory area, the first 8 bits are used. all unused rom addresses will be read as ?0?. note: rom address 3fh is unused. an attempt to access this address is recognized as a communication line error (?data-in stuck to v cc ?) all internal registers will be cleared (software reset).
spi control and status register L99MD02 30/46 doc id 16082 rev 5 7 spi control and status register table 22. ram memory map address name access content 01h control register 1 read/write output switch on/off 02h control register 2 read/write not used 03h control register 3 read/write low side high current mode v s configuration 04h control register 4 read/write current multiplexer 05h control register 5 read/write pwm 06h control register 6 read/write open-load 10h status register 0 read only overcurrent 11h status register 1 read only open-load 12h status register 2 read only tsd over/undervoltage table 23. rom memory map (access with oc0 and oc1 set to ?1?) address name access content 00h id header read only 43h (device class assp, 2 additional information bytes) 01h version read only 00h (engineering samples) (st-spi) 02h produccode1 read only 3eh (62 st_spi) 03h produccode2 read only 4eh (n st_spi) 3dh fuses read only fuse data 9 -0 3eh spi-frame id read only 02h spi-frame-id register (24 bit st_spi)
L99MD02 spi control and status register doc id 16082 rev 5 31/46 table 24. control status register (1) address access data byte 1 data byte 0 output switch on/off 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01h r/w 0 0 hs4 ls4 hs6 ls6 hs5 ls5 0 0 hs3 ls3 hs2 ls2 hs1 ls1 not used 02h r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 low side high current (reset value = 1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 03h r/w 0 hc4 hc6 hc5 0 hc3 hc2 hc1 0 v s ov warn/ shutdown 0 0 0 0 0 0 current multiplexer 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 04h r/w outx to curr2 outx to curr2 outx to curr2 enable curr2 outx to curr1 outx to curr1 outx to curr1 enable curr1 0 0 0 0 2kfact 2kfac t 1kfact 1kfac t pwm 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 05h r/w 0 0 0 0 0 0 pwm duty 0 out4 out6 out5 0 out3 out2 out1 open-load 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 06hr/w000000000 disable ol4 disable ol6 disable ol5 0 disable ol3 disable ol2 disable ol1 status overcurrent 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10h r 0 0 hs4 ls4 hs6 ls6 hs5 ls5 0 0 hs3 ls3 hs2 ls2 hs1 ls1 status open-load 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11h r 0 0 0 0 0 0 0 0 0 out4 out6 out5 0 out3 out2 out1 status tsd; over/undervoltage 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 12h r 0 0 0 0 0 0 0 0 tsd tsd warm 00 v s uv v s ov v sb uv v sa uv 1. default reset value is 0, all unused bits read 0, unused bits have to be set to 0.
spi control and status register L99MD02 32/46 doc id 16082 rev 5 table 25. control register 1 (read/write); address 01h bit name comment 15 if a bit is set, the selected output driver is switched on. if the corresponding pwm enable bit is set the driver will be pwmed. if the bits of hs-and ls-driver of the same half bridge are set, the hs and the ls-driver will be deactivated. 14 13 out4 ? hs on/off 12 out4 ? ls on/off 11 out6 ? hs on/off 10 out6 ? ls on/off 9 out5 ? hs on/off 8 out5 ? ls on/off 7 6 5 out3 ? hs on/off 4 out3 ? ls on/off 3 out2 ? hs on/off 2 out2 ? ls on/off 1 out1 ? hs on/off 0 out1 ? ls on/off table 26. control register 3 (read/write); address 03h bit name comment 15 high current mode of low side switch ?0?: the selected low side switch is in low current mode. the overcurrent and open-load thresholds are reduced by ?. the selected current monitor ratio is doubled. ?1? (default setting) the selected low side switch is in high current mode. 14 high current ls 4 13 high current ls 6 12 high current ls 5 11 10 high current ls 3 9 high current ls 2 8 high current ls 1 7 - 6 v s ov shutdown/warn in case of v s overvoltage ?0?: all outputs will be switched off + status bit set. ?1?: only status bit will be set. 5 4 3
L99MD02 spi control and status register doc id 16082 rev 5 33/46 2 1 0 table 27. control register 4 (read/write); address 04h bit name comment 15 outx to curr2 bit2 bit setting 111 110 101 100 011 010 001 000 14 outx to curr2 bit1 to curr2 out4 out6 out5 out3 out2 out1 13 outx to curr2 bit0 12 enable curr2 enable the current monitor output 2 11 outx to curr1 bit2 bit setting 111 110 101 100 011 010 001 000 10 outx to curr1 bit1 to curr1 out4 out6 out5 out3 out2 out1 9 outx to curr1 bit0 8 enable curr1 enable the current monitor output 1 7 - 6 - 5 - 4 - 3 curr2 k-factor current monitor ratio i outx /i curr if th e high current bit (register 03h) is set to 0 the ratio for the low side will be the double of the programmed one. 2 curr2 k-factor 1 curr1 k-factor 0 curr1 k-factor table 28. ratio for curr2 bit3 bit2 ratio for curr2 0 0 1/1000 0 1 1/750 1 0 1/500 1 1 1/250 table 26. control register 3 (read/write); address 03h (continued) bit name comment
spi control and status register L99MD02 34/46 doc id 16082 rev 5 table 29. ratio for curr1 bit1 bit0 ratio for curr1 0 0 1/1000 0 1 1/750 1 0 1/500 1 1 1/250 table 30. control register 5 (read/write); address 05h bit name comment 15 - 14 - 13 - 12 - bit 9 bit 8 pwm duty cycle 11 - 0 0 15 % 10 - 0 1 30 % 9 pwm duty bit1 1 0 45 % 8 pwm duty bit0 1 1 60 % 7 - pwm enable: ? ?0?: pwm disabled this output ? ?1?: if the corresponding enable bit is set and the pwm bit is set to ?1? the programmed output will be pwm?ed with typical 100 hz 6 pwm to out4 5 pwm to out6 4 pwm to out5 3 - 2 pwm to out3 1 pwm to out2 0 pwm to out1
L99MD02 spi control and status register doc id 16082 rev 5 35/46 table 31. control register 6 (read/write); address 06h bit name comment 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 disable the open-load measurement ?0?: open-load is signaled via the corresponding bit in status register 2 and the global error byte. ?1?: in case of an open-load, no register will change. also the global error register will not change. 6 disable ol out4 5 disable ol out6 4 disable ol out5 3 2 disable ol out3 1 disable ol out2 0 disable ol out1 table 32. status register 0 (read only); address 10h bit name comment 15 - overcurrent error detected, driver will be deactivated 14 - 13 hs4 12 ls4 11 hs6 10 ls6 9 hs5 8 ls5 7 - 6 - 5 hs3 4 ls3 3 hs2 2 ls2 1 hs1 0 ls1
spi control and status register L99MD02 36/46 doc id 16082 rev 5 table 33. status register 1 (read only); address 11h bit name comment 15-8 - - 7 - open-load detected, information only no changes if the corresponding disable ol bit (control register 6) is set 6 open-load out4 5 open-load out6 4 open-load out5 3 2 open-load out3 1 open-load out2 0 open-load out1 table 34. status register 2 (read only); address 12h bit name comment 15-8 - - 7 tsd overtemperature detected: all the drivers are switched off 6 tsd warning overtemperature warning level detected, information only 5 - 4 - 3 v s uv v s undervoltage 2 v s ov v s overvoltage 1 v sb uv v sb undervoltage 0 v sa uv v sa undervoltage
L99MD02 application examples doc id 16082 rev 5 37/46 8 application examples figure 10. driving 3 dc-motors simultaneously 0lfur 9rowdjhprqlwrulqj /rjlf 63, 08; (1 &61 6&. ', '2 &85 &85 0 0 0 9ff 99 9 6 9 6$ 9 6% 2xw 2xw 2xw 2xw 2xw 2xw 9 6 *1' *$3*06
application examples L99MD02 38/46 doc id 16082 rev 5 figure 11. driving 5 dc-motors sequentially 0lfur 9rowdjhprqlwrulqj /rjlf 63, 08; (1 &61 6&. ', '2 &85 &85 9ff 99 9 6 9 6$ 9 6% 2xw 2xw 2xw 2xw 2xw 2xw 9 6 0 0 0 0 0 *1' *$3*06
L99MD02 package and pcb thermal data doc id 16082 rev 5 39/46 9 package and pcb thermal data 9.1 powersso-36 thermal data figure 12. powersso-36 pc board $*9 note: board finish thickness 1.6 mm +/- 10%; board double layer and four layers; board dimension 129 mm x 60 mm; board material fr4; cu thickness 0.070 mm (outer layers); cu thickness 0.035mm (inner layers); thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/-0.08 mm; cu thickness on vias 0.025 mm; footprint dimension 4.1 mm x 6.5 mm
package and pcb thermal data L99MD02 40/46 doc id 16082 rev 5 figure 13. powersso-36 thermal impedance junction ambient =7+? &: 7lphv )rrwsulqw fp /d\hu $*9
L99MD02 package information doc id 16082 rev 5 41/46 10 package information 10.1 ecopack ? package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 10.2 powersso-36? mechanical data figure 14. powersso-36? package dimensions a g00066v1
package information L99MD02 42/46 doc id 16082 rev 5 l table 35. powersso-36 mechanical data symbol millimeters min. typ. max. a2.15 - 2.45 a2 2.15 - 2.35 a1 0 - 0.1 b0.18 - 0.36 c0.23-0.32 d (1) 1. ?d? and ?e? do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side (0.006?). 10.10 - 10.50 e 7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 g1 - - 0.06 h10.1 - 10.5 h- -0.4 k0-8 l0.55 - 0.85 m-4.3- n - - 10 o-1.2- q-0.8- s-2.9- t-3.65- u-1- x 4.3 - 5.2 y 6.9 - 7.5
L99MD02 package information doc id 16082 rev 5 43/46 10.3 packing information figure 15. powersso-36 tube shipment (no suffix) figure 16. powersso-36 tape and reel shipment (suffix ?tr?) a c b gapgcft00002 all dimensions are in mm. base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed gapgcft00003
revision history L99MD02 44/46 doc id 16082 rev 5 11 revision history table 36. document revision history date revision changes 30-jul-2009 1 initial release. 21-jun-2010 2 updated features list. removed block diagram on page 1. updated figure 1: detailed block diagram . updated section 2.3: standby mode . chapter 3: pin definitions and functions : ? updated table 3: pin description ? updated figure 3: pin connection (top view-not in scale) updated table 16: dynamic characteristics and table 24: control status register . inserted table 30: control register 5 (read/write); address 05h added chapter 10: package information . 25-jan-2011 3 updated figure 2: power on reset updated features list. table 9: over and undervoltage detection ?v suv off , v suv on , v sauv on , v sbuv off , v sbuv on : updated maximun value ?v suv hyst , v sauv hyst , v sbuv hyst , v sov hyst : added minimum value ?v sauv off : updated minimum and maximum values table 10: switches ? updated following parameters: r onlslc 1-6 , : t d lh /t d lh , i qlh , i qll , i oldhs1-6 , i oldlshc1-6 , i oldlslc1-6 table 11: current monitor output ? updated i curr1/2 acc parameter added table 12: current monitor dynamic characteristics updated following tables: ? table 25: control register 1 (read/write); address 01h ? table 26: control register 3 (read/write); address 03h ? table 27: control register 4 (read/write); address 04h ? table 30: control register 5 (read/write); address 05h ? table 31: control register 6 (read/write); address 06h ? table 32: status register 0 (read only); address 10h ? table 33: status register 1 (read only); address 11h added chapter 9: package and pcb thermal data
L99MD02 revision history doc id 16082 rev 5 45/46 23-feb-2011 4 updated features list. updated section 2.2: power supply: v sa , v sb updated following tables: ? table 3: pin description ? table 11: current monitor output ? table 12: current monitor dynamic characteristics ? table 16: dynamic characteristics ? table 20: global status byte 19-sep-2013 5 updated disclaimer. table 36. document revision history (continued) date revision changes
L99MD02 46/46 doc id 16082 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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